Library ieee;useieee.stdlogic1164. All;entityshiftsiso isport(Clock, Sin: in stdlogic;Sout: out stdlogic);endshiftsiso;architecturebehav of shiftsiso issignaltemp: stdlogicvector(7 downto 0);beginprocess (Clock)beginif(Clock'event and Clock='1') thenfori in 0 to 6 looptemp(i+1). Library ieee;useieee.stdlogic1164. All;entityshiftsiso isport(Clock, Sin, Clear: in stdlogic;Sout: out stdlogic);endshiftsiso;architecturebehav of shiftsiso issignaltemp: stdlogicvector(7 downto 0);beginprocess(Clock, Clear)beginif (Clear='1') thentemp '0');elsif(Clock' event and Clock='1') thentemp. Library ieee;useieee.stdlogic1164.
4 Bit Shift Register Using Jk Flip Flop
All;entityshiftSS isport(Clock, Sin, Set: in stdlogic;Sout: out stdlogic);endshiftSS;architecture behav of shiftSS issignaltemp: stdlogicvector(7 downto 0);beginprocess (Clock, Set)beginif(Clock'event and Clock='1') thenif(Set='1') thentemp '1');elsetemp. Library ieee;useieee.stdlogic1164. All;entityshiftsipo isport(Clock, Sin: in stdlogic;Pout: out stdlogicvector(7 downto0));endshiftsipo;architectureexam of shiftsipo issignaltemp: stdlogicvector(7 downto 0);beginprocess(Clock)beginif(Clock'event and Clock='1') thentemp.
You associate FPGA I/O to HDL nets in another file that is part of your project. For Xilinx development using the ISE software, that file is called the 'UCF' file. In Xilinx Vivado they changed the format and extension of that file (it is more of a pain in the ass now, IMO). If this is for Altera, I don't know, but I'm sure it is similar.Also, using a push-button for a clock is going to give you fits if the button is not hardware debounced (since I don't see any HDL debounce in that screen shot).